B.Tech -Electronics and Communication Engg.
(2015-present)
JSSATEN (AKTU)
Aggregate - 81%
Intermediate 10+2
(2013-14)
DMA-1 (CBSE)
Aggregate - 90%
High school
(2011-12)
DMA-1 (CBSE)
Aggregate - 95%
Digital Design in Verilog
Matlab + Simulink
VLSI
Signals and Systems
Control Systems
Data Structures & Algorithm
Digital Signal Processing
Digital Communication
Embedded Intern
BotLabs, TBIU, IIT-Delhi
(6-months: 20 July'18 - Current)
Intern/trainee at National Informatics Centre (NIC)-Delhi, India
(6-weeks: June'18 - July'18)
VLSI trainee
Dkop Labs, Noida
(6-weeks: July'18-Aug'18)